1. Field of the Invention
The present invention relates to a method for fabricating a transistor and a structure thereof, and more particularly to a method for fabricating a gate electrode of a metal oxide semiconductor (MOS) transistor and a structure thereof.
2. Background of Related Art
A conventional transistor fabricated on a semiconductor substrate, in particular a conventional transistor with a thin gate insulation layer, has a disadvantage in that leakage current which flows between the source and drain regions increases while a turn-off voltage is applied to a gate electrode. This problem is caused by an electric field which forms in the channel region toward the gate electrode from the drain (or source) region to which a voltage higher than a voltage supplied to the gate electrode is applied. Such a problem is more serious in a transistor formed such that a channel region is adjacent to the source and drain regions formed by self-aligning the gate electrode with the source and drain regions.
FIG. 1A shows a conventional thin film MOS transistor. In the transistor, source and drain regions 10b, 10c are self-aligned with a gate electrode 14. FIG. 1B shows another conventional thin film MOS transistor having an offset resistance structure with an offset resistance being formed by the distance between the source and drain regions and an enlarged channel region.
Referring to FIG. 1A, a gate insulation layer 12 and a gate electrode 14 are formed on an active layer 10 made of polycrystalline silicon or amorphous silicon. A region positioned under the gate insulation layer 12 operates as a channel region 10a. The regions adjacent to of the channel region 10a are the source and drain regions 10b, 10c, which are subjected to an ion-implantation so as to operate as a source region 10b and a drain region 10c, respectively. The source and drain regions 10b and 10c are subjected to the ion-implantation by using the gate electrode 14 as a mask, and therefore, the locations of the source and drain regions are self-aligned with the gate electrode 14. Prior art which discloses such a conventional self-aligned structure is disclosed in U.S. Pat. No. 4,597,160, which issued in 1986.
However, in the conventional transistor which has a self-aligned source and drain region 10b, 10c, the channel region 10a is positioned directly under the gate electrode and is therefore adjacent to the source and drain regions 10b, 10c. This allows the formation of an electric field between the channel region and the drain (or source) region 10b, 10c when receiving a predetermined voltage and between the channel region and the gate electrode when receiving a turn-off voltage which is lower than the predetermined voltage applied to the drain or source region 10b, 10c. This electric field transmits an exicited energy to the carriers which are trapped within a depletion region formed between the source or drain region and the channel region. As a result, the excited carriers deviate from the depletion region and produce a leakage current. Consequently, when the turn-off voltage is applied to the gate electrode, a leakage current, which always flows between the source and drain regions 10b, 10c, increases.
To solve such a problem of the conventional MOS transistor, an offset resistance structure has been proposed which separates the channel region from the source and drain regions by a predetermined distance.
Referring to FIG. 1B, a conventional thin film MOS transistor having an offset resistance structure is shown. The MOS transistor has a gate insulation layer 18 and a gate electrode 20 formed on an active layer 16. The left and right regions of the active layer 16 as depicted in FIG. 1B are doped to form a source region 16b and a drain region 16c, while region positioned under the gate insulation layer 18 functions as a channel region 16a. The total length of the undoped regions 16d, 16a, 16e of the active layer 16 between the source and drain regions 16b and 16c is longer than that under the gate electrode 20. The resistances of the undoped regions 16d, 16e positioned respectively between the channel region 16a and the source and drain regions 16b and 16c function as an offset resistance to reduce leakage current. Since the gate electrode 20 is separated from the source and drain regions 16b, 16c, the influence of an electric field which forms between the gate electrode 20 and the source (or drain) regions 16b, 16c is reduced. As a result, the leakage current between the gate electrode 20 and the source or drain regions 16b, 16c decreases.
However, in order to fabricate the conventional MOS transistor having the conventional offset resistance structure as shown in FIG. 1B, an additional photo lithographic process is needed. Hence, the offset resistance structure is disadvantageous because the process by which it is formed is complicated as compared with the conventional self-aligning process, and the cost of manufacturing thereof rises. Further, since the channel region 16a is separated from the source and drain regions, the turn-on current through the channel 16a is reduced when a turn-on voltage is applied to the gate electrode 20. Thus, the conventional offset resistance structure suffers from a further disadvantage in that the gate driving force is lowered.